1. Techinical Field
The present disclosure relates to a semiconductor memory device and method of operating the same and, more particularly, to a semiconductor memory device and method of operating the same that can improve a refresh characteristic by replacing a fail word line with a redundant word line.
2. Discussion of Related Art
If even one of numerous cells is defective, the entire memory is classified as inferior and not used. As the level of integration of the memory is increased, the likelihood of a defect generated in a few cells is high. To classify an entire memory as inferior and not use it is an inefficient method that lowers yield. To solve this problem, redundant memory cells are provided with the memory. The defective or fail cell is replaced by the redundant memory cell when the failure takes place in the cell, thus improving the yield.
FIG. 1 shows a cell array structure of a semiconductor memory device having normal cells and redundant cells.
Referring to FIG. 1, the memory device includes a normal memory block NMB having a plurality of normal word lines (for example, 256 in number; NWL0 to NWL255 shown) for storing data, and a redundant memory block RMB having a plurality of redundant word lines (for example, 256 in number; RWL0 to RWL255 shown) for substituting fail normal word lines of the normal memory block NMB.
After such a memory device is fabricated, whether a fail cell has occurred is finally checked through a test. If there is a fail cell (for example, C100) of the memory cells included in the normal memory block NMB, the fuse of the fuse ROM array (not shown) included in the memory device is cut to store address information (hereinafter referred to as ‘fail address’) on a normal word line NWL0 to which the fail cell C100 is connected. Such address information on the fail normal word line NWL0 is compared with an external address (or internal address that is internally generated for a refresh operation) externally inputted every time when the memory device is operated. As a result of the comparison, if the fail address and the external address (or the internal address) are not coincident, it means that the normal word line (for example, one of NWL1 to NWL255) does not have any fail cell. Therefore, a corresponding normal word line is selected and driven. If the fail address and the external address (or the internal address) are coincident, it means that the normal word line NWL0 has a fail cell. Accordingly, a signal inputted to the corresponding normal word line NWL0 is applied to the redundant word line (for example, RWL0) of the redundant memory block RMB, thus driving the redundant word line RWL0.
In the case of a memory cell having a single transistor and a single capacitor, charges may be stored at the capacitor. To increase the level of integration, the size of the capacitor may be decreased, thereby increasing the amount of time charges stored at the capacitor are discharged. Thus, difficulty may exist in maintaining data for an extended period of time. To maintain data stored at the memory cell for a long period of time, the memory cell performs a refresh operation for restoring data stored at the memory cell.
To read data stored at the memory cell, as well as during a refresh operation, the normal word line NWL0 to which the corresponding memory cell (for example, C100) is connected is selected, and a voltage is detected through a bit line connected to the memory cell C100. If the memory cell C100 is a defective or fail memory cell, as discussed above, the redundant word line RWL0 is selected instead of the normal word line NWL0, and data stored at the memory cell C110 connected to the redundant word line RWL0 are read therefrom. To read data stored at the memory cell C100 connected to the redundant word line RWL0, a sense amplifier BLSA1 compares the voltage detected through a bit line BL1 and a reference. voltage (generally, Vcc/2) applied to an inverse bit line BL1#.
If a charge of ‘0’ is stored at the capacitor of the memory cell C110, data can be maintained stably in the memory cell since there are no charges to be discharged. Further, because the difference in the voltages between the bit line BL1 of 0 v and the inverse bit line BL1# of Vcc/2 during a refresh or read operation is clearly distinguished, a read error rarely takes place. If a charge of ‘1’ is stored at the capacitor of the memory cell C110, however, it may be impossible to maintain the data in the memory cell stably since the charges are discharged as time elapses. Therefore, during a refresh or read operation, the sense amplifier BLSA1 may detect the difference in the voltages (α) between the bit line BL1 and the inverse bit line BL1# to be about α+Vcc/2 lower than Vcc due to the discharge and the reference voltage applied to the inverse bit line BL1# of Vcc/2. As a result of the comparison, if the difference in the voltages (α) is not high, a read error may occur.
As the level of integration increases, the capacitance of the capacitor may decrease, thereby increasing the speed that the charges stored at the capacitor are discharged. Therefore, even if a fail word line is replaced with a redundant word line, it is not guaranteed that data stored in the memory cell can be maintained stably. Furthermore, it may become more difficult for the sense amplifier to detect the difference in the voltages between the bit line and the inverse bit line. Therefore, the probability that a read error may occur is increased, thereby lowering the reliability of the device.